Profile
Spacecraft Electronics & Power Systems Engineer with 5 years of flight-proven experience delivering EPS and PCDU hardware for operational LEO constellations. Specialises in high-reliability PCB design, DC-DC converter design and stability analysis, radiation-tolerant COTS component qualification, and satellite bus power architecture. Experienced across the full hardware lifecycle - from architecture and schematic design through EM/FM build and on-orbit commissioning - with a strong foundation in ECSS/NASA standards, FMECA, and fault-tolerant topologies.
Technical Skills
| EPS & Power Architecture |
EPS/PCDU architecture, power budgeting, fault-tolerant and redundant topologies, battery and solar array sizing, satellite bus power distribution |
| Power Electronics Design |
DC-DC converters (buck, SEPIC, PSFB), custom power switches, motor drivers for AOCS actuators |
| PCB & Hardware Design |
Multilayer PCB design and review (personally designed through 4-layer; reviewed higher complexity), schematic capture, IPC Class 3 flight standards, ISRO PAX layout standard, BOM management, EM/FM build and bring-up |
| Radiation & Reliability |
TID/SEE environment analysis, COTS component qualification using published radiation data (CERN, DOE, IUAC, NASA), FMECA, FDIR |
| Simulation & Analysis |
Circuit simulation (LTSpice, TINA, PSpice), Bode plot and loop stability analysis, worst-case circuit analysis (WCCA), orbit propagation (Orekit), radiation dose modelling (SHIELDOSE-2) |
| EMI/EMC & Grounding |
EMI filter design (basic), spacecraft grounding architecture per NASA-HDBK-4001, shielding schemes, ECSS/NASA/ISRO EMC compliance |
| Standards & Process |
ECSS, NASA NPR 7123, NASA-HDBK-4001, ISRO standards; requirements definition and traceability; design reviews (PDR, CDR, TRR, FRR) |
| Tools |
KiCad, OrCAD, Altium, LTSpice, TINA, Python, C, Bash, Git, Linux |
Experience
Pixxel · Bangalore, India
- Leading EPS and PCDU architecture and design for an 8-satellite sub-200 kg EO constellation, driving all design decisions from power budget through fault-tolerant topology selection, in compliance with ECSS/NASA/ISRO standards across PDR, CDR, TRR, and FRR.
- Designing gyroscope package board electronics around the NXP S32K344 MCU, owning architecture definition, schematic design, and BOM closure; targeting hardware completion April 2026.
- Conducted radiation environment trade studies (TID, SEE) using published data from CERN, DOE, and IUAC; qualified COTS components as radiation-tolerant alternatives for a 30 krad (Si) unshielded environment (reduced to ~1 krad at component level via enclosure shielding for a 5-year mission), cutting component costs by over 90% and reducing hardware lead times from 16–18 weeks to under 3 weeks.
- Enhanced spacecraft bus power architecture by implementing redundant, fault-tolerant converter topologies, raising end-to-end conversion efficiency from 85% to 93%.
- Developed an EPS performance monitoring and requirements traceability tool in Python, supporting V&V closure across TVAC, vibration, and system integration campaigns.
- Coordinated with ISRO, vendors, and manufacturers on supply chain alignment, regulatory compliance, and mission-critical schedule milestones.
Pixxel · Bangalore, India
- Designed end-to-end EPS and PCDU for the Firefly LEO constellation (6 satellites, 5-year mission), powering payloads, sensors, and AOCS actuators - delivered with zero major power anomalies during on-orbit commissioning.
- Designed DC-DC buck converters, custom power switches, and motor drivers for AOCS actuators; achieved 10–12% efficiency improvement through topology selection and component optimisation.
- Performed loop stability analysis (Bode plots, phase and gain margin) on flight converter designs; validated compensation networks to meet ECSS stability margin requirements.
- Led COTS component selection and radiation-tolerance qualification for flight hardware, compressing procurement lead times and enabling schedule adherence across multiple satellite launches.
- Defined and implemented spacecraft grounding architecture per NASA-HDBK-4001 and applied EMI filter design in compliance with ECSS/NASA standards, measurably reducing integration anomalies.
- Oversaw multilayer PCB design for IPC Class 3 flight boards; personally executed schematic design and 4-layer board design, reviewed layouts against ISRO PAX and ECSS requirements.
- Transitioned prototypes to EM and FM flight hardware; led FMECA for EPS and spacecraft power subsystems, enabling fault-tolerant FDIR implementation.
- Oversaw V&V campaigns (board bring-up, Bode analysis, TVAC, vibration) and mission operations readiness (DITL simulations, full dress rehearsals), translating test data into design decisions to drive V&V closure.
Pixxel · Bangalore, India
- Simulated and validated protection circuits (UVLO, OVLO, latch-up limiters, power monitoring) for space-grade EPS designs using LTSpice and TINA.
- Supported EM prototype bring-up, gaining foundational experience in power subsystem reliability and space hardware processes.
Projects
End-to-end satellite power and radiation analysis tool built in Python and Streamlit. Uses Orekit for orbit propagation, SHIELDOSE-2 for TID calculations, and AP-8/AE-8 trapped particle models. Covers battery and solar array sizing, operational mode power profiles, eclipse/sunlight duration, and radiation effects (TID, DD, SEE) for LEO missions.
True 3D volumetric display using persistence-of-vision technology. ESP32-S3 Mini rotor controller driving an 8×12 APA102C LED matrix; STM32G031 base station; wireless power transfer to the spinning rotor. Key challenges include high-speed power delivery to a rotating assembly and precise rotational synchronisation.
Personal design of a phase-shifted full-bridge SMPS targeting 300 W output. Design covers converter topology, synchronous rectification, and closed-loop compensation. Intended as an openly published reference design.
End-to-end electronics and mechanical design of a custom keyboard: ESP32-S3 MCU, IPS display integration, Cherry MX switch matrix, custom PCB, and bespoke enclosure. Demonstrates full design-cycle ownership from schematic through mechanical integration and firmware.
Education
Inderprastha Engineering College, AKTU · India
Relevant coursework: Power Electronics, Digital System Design, Embedded Systems, Communication Systems
Award: Best Paper, NCRTEE 2020 - 8-bit Microcomputer using discrete ICs (28C16 EEPROM, 74189 RAM)